Description
SN65LVDS301ZXHR Texas Instruments - Yeehing Electronics
Programmable 27-bit display serial interface transmitter
Pricing (USD)
| Quantity | Unit Price |
| 1 — 99 | 3.466 |
| 100 — 249 | 3.037 |
| 250 — 999 | 2.13 |
| 1,000 + | 1.37 |
The above prices are for reference only.
Specifications
For more information, please refer to datasheet
Documents
| SN65LVDS301ZXHR Datasheet |
More Information
The SN65LVDS301 serializer device converts 27 parallel data inputs to 1, 2, or 3 Sub Low-Voltage Differential Signaling (SubLVDS) serial outputs. It loads a shift register with 24 pixel bits and 3 control bits from the parallel CMOS input interface. In addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. Each word is latched into the device by the pixel clock (PCLK). The parity bit (odd parity) allows a receiver to detect single bit errors. The serial shift register is uploaded at 30, 15, or 10 times the pixel-clock data rate depending on the number of serial links used. A copy of the pixel clock is output on a separate differential output.
