ADC08500CIYB/NOPB


YeeHing #: Y004-ADC08500CIYB/NOPB
Inventory: 3800

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Description

ADC08500CIYB/NOPB Texas Instruments - Yeehing Electronics

8-Bit, 500-MSPS Analog-to-Digital Converter (ADC)

Pricing (USD)

Quantity Unit Price
1 — 99 50.652
100 — 249 45.024
250 — 999 37.013
1,000 + 23.17

The above prices are for reference only.

Specifications

Manufacturer Texas Instruments
Product Category Analog to Digital Converters - ADC
RoHS Y
Series ADC08500
Mounting Style SMD/SMT
Package / Case LQFP-EP-128
Resolution 8 bit
Number of Channels 1 Channel
Sampling Rate 500 MS/s
Input Type Differential
Interface Type Serial
Architecture Folding Interpolating
Reference Type Internal
Analog Supply Voltage 1.9 V
Digital Supply Voltage 1.8 V to 2 V
SNR - Signal to Noise Ratio 48 dB
Minimum Operating Temperature - 40 C
Maximum Operating Temperature + 85 C
Packaging Tray
Features Low Power
Height 1.4 mm
Input Voltage 0.65 V, 0.87 V
Length 20 mm
Number of Converters 1 Converter
Output Type LVDS
Power Consumption 800 mW
Product Analog to Digital Converters
Type ADC
Width 20 mm
Brand Texas Instruments
DNL - Differential Nonlinearity +/- 0.15 LSB
ENOB - Effective Number of Bits 7.5 Bit
Gain Error 25 mV
INL - Integral Nonlinearity 0.9 LSB
Moisture Sensitive Yes
Number of ADC Inputs 1 Input
Operating Supply Voltage 1.9 V
Pd - Power Dissipation 2 W
Product Type ADCs - Analog to Digital Converters
Sample and Hold Yes
SFDR - Spurious Free Dynamic Range 56 dB
SINAD - Signal to Noise and Distortion Ratio 47 dB
Factory Pack Quantity 60
Subcategory Data Converter ICs
Unit Weight 0.042350 oz

For more information, please refer to datasheet

Documents

ADC08500CIYB/NOPB Datasheet

More Information

The ADC08500 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 0.8 Watts at 500 MSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

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