Description
ADC12C105CISQ/NOPB Texas Instruments - Yeehing Electronics
12-Bit, 105-MSPS, 1.0-GHz Input Bandwidth Analog-to-Digital Converter (ADC)
Pricing (USD)
| Quantity | Unit Price |
| 1 — 99 | 39.099 |
| 100 — 249 | 34.755 |
| 250 — 999 | 28.57 |
| 1,000 + | 17.89 |
The above prices are for reference only.
Specifications
| Manufacturer | Texas Instruments |
| Product Category | Analog to Digital Converters - ADC |
| RoHS | Y |
| Series | ADC12C105 |
| Mounting Style | SMD/SMT |
| Package / Case | WQFN-32 |
| Resolution | 12 bit |
| Number of Channels | 1 Channel |
| Sampling Rate | 105 MS/s |
| Input Type | Differential |
| Interface Type | Parallel |
| Architecture | Pipeline |
| Reference Type | External, Internal |
| Analog Supply Voltage | 2.7 V to 3.6 V |
| Digital Supply Voltage | 2.4 V to 3.6 V |
| SNR - Signal to Noise Ratio | 70.1 dB |
| Minimum Operating Temperature | - 40 C |
| Maximum Operating Temperature | + 85 C |
| Packaging | Reel |
| Features | Low Power |
| Height | 0.8 mm |
| Input Voltage | 2 V |
| Length | 5 mm |
| Number of Converters | 1 Converter |
| Power Consumption | 400 mW |
| Type | S/H ADC |
| Width | 5 mm |
| Brand | Texas Instruments |
| DNL - Differential Nonlinearity | +/- 0.7 LSB |
| ENOB - Effective Number of Bits | 11.1 Bit |
| INL - Integral Nonlinearity | 0.5 LSB |
| Moisture Sensitive | Yes |
| Number of ADC Inputs | 1 Input |
| Operating Supply Voltage | 3.3 V |
| Pd - Power Dissipation | 400 mW |
| Product Type | ADCs - Analog to Digital Converters |
| Sample and Hold | Yes |
| SFDR - Spurious Free Dynamic Range | 82 dB |
| SINAD - Signal to Noise and Distortion Ratio | 68.6 dB |
| Factory Pack Quantity | 1000 |
| Subcategory | Data Converter ICs |
For more information, please refer to datasheet
Documents
| ADC12C105CISQ/NOPB Datasheet |
More Information
The ADC12C105 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12C105 may be operated from a single +3.0V or +3.3V power supply and consumes low power.
