Description
ADC3222IRGZT Texas Instruments - Yeehing Electronics
Dual-Channel, 12-Bit, 50-MSPS Analog-to-Digital Converter (ADC)
Pricing (USD)
| Quantity | Unit Price |
| 1 — 99 | 18.877 |
| 100 — 249 | 16.78 |
| 250 — 999 | 13.794 |
| 1,000 + | 8.64 |
The above prices are for reference only.
Specifications
| Manufacturer | Texas Instruments |
| Product Category | Analog to Digital Converters - ADC |
| RoHS | Y |
| Series | ADC3222 |
| Mounting Style | SMD/SMT |
| Package / Case | VQFN-48 |
| Resolution | 12 bit |
| Number of Channels | 2 Channel |
| Sampling Rate | 50 MS/s |
| Input Type | Differential/Single-Ended |
| Interface Type | Serial LVDS |
| Architecture | Pipeline |
| Reference Type | External, Internal |
| Analog Supply Voltage | 1.7 V to 1.9 V |
| SNR - Signal to Noise Ratio | 71 dB |
| Minimum Operating Temperature | - 40 C |
| Maximum Operating Temperature | + 85 C |
| Packaging | Reel |
| Features | Low Power |
| Number of Converters | 2 Converter |
| Power Consumption | 148 mW |
| Type | General Purpose |
| Brand | Texas Instruments |
| Shutdown | Shutdown |
| ENOB - Effective Number of Bits | 11.5 Bit |
| Moisture Sensitive | Yes |
| Product Type | ADCs - Analog to Digital Converters |
| Reference Voltage | 1.8 V |
| SFDR - Spurious Free Dynamic Range | 90 dB |
| SINAD - Signal to Noise and Distortion Ratio | 70.9 dB |
| Factory Pack Quantity | 250 |
| Subcategory | Data Converter ICs |
| THD - Total Harmonic Distortion | 85 dBc |
| Unit Weight | 0.005228 oz |
For more information, please refer to datasheet
Documents
| ADC3222IRGZT Datasheet |
More Information
The ADC322x are a high-linearity, ultra-low power, dual-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC322x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
