Description
ADC3243IRGZT Texas Instruments - Yeehing Electronics
Dual-Channel, 14-Bit, 80-MSPS Analog-to-Digital Converter (ADC)
Pricing (USD)
| Quantity | Unit Price |
| 1 — 99 | 39.345 |
| 100 — 249 | 34.974 |
| 250 — 999 | 28.75 |
| 1,000 + | 18.00 |
The above prices are for reference only.
Specifications
| Manufacturer | Texas Instruments |
| Product Category | Analog to Digital Converters - ADC |
| RoHS | Y |
| Series | ADC3243 |
| Mounting Style | SMD/SMT |
| Package / Case | VQFN-48 |
| Resolution | 14 bit |
| Sampling Rate | 125 MS/s |
| Interface Type | Serial LVDS |
| Architecture | Pipeline |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V |
| Minimum Operating Temperature | - 40 C |
| Maximum Operating Temperature | + 85 C |
| Packaging | Reel |
| Features | Low Power |
| Power Consumption | 183 mW |
| Brand | Texas Instruments |
| ENOB - Effective Number of Bits | 11.9 Bit |
| Moisture Sensitive | Yes |
| Product Type | ADCs - Analog to Digital Converters |
| SFDR - Spurious Free Dynamic Range | 93 dB |
| SINAD - Signal to Noise and Distortion Ratio | 73.3 dB |
| Factory Pack Quantity | 250 |
| Subcategory | Data Converter ICs |
For more information, please refer to datasheet
Documents
| ADC3243IRGZT Datasheet |
More Information
The ADC324x are a high-linearity, ultra-low power, dual-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC324x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
