Description
ADC32J25IRGZT Texas Instruments - Yeehing Electronics
Dual-Channel, 12-Bit, 160-MSPS Analog-to-Digital Converter (ADC)
Pricing (USD)
Quantity | Unit Price |
1 — 99 | 43.492 |
100 — 249 | 38.659 |
250 — 999 | 31.78 |
1,000 + | 19.90 |
The above prices are for reference only.
Specifications
Manufacturer | Texas Instruments |
Product Category | Analog to Digital Converters - ADC |
RoHS | Y |
Series | ADC32J25 |
Mounting Style | SMD/SMT |
Package / Case | VQFN-48 |
Resolution | 12 bit |
Number of Channels | 2 Channel |
Sampling Rate | 160 MS/s |
Input Type | Differential/Single-Ended |
Interface Type | JESD204B |
Architecture | Pipeline |
Reference Type | External, Internal |
Analog Supply Voltage | 1.8 V |
Digital Supply Voltage | 1.8 V |
SNR - Signal to Noise Ratio | 67.8 dB |
Minimum Operating Temperature | - 40 C |
Maximum Operating Temperature | + 85 C |
Packaging | Reel |
Features | Low Power |
Height | 1 mm |
Length | 7.15 mm |
Number of Converters | 2 Converter |
Output Type | CML |
Power Consumption | 454 mW |
Type | High Speed ADC |
Width | 7.15 mm |
Brand | Texas Instruments |
Shutdown | No Shutdown |
DNL - Differential Nonlinearity | 0.1 LSB |
ENOB - Effective Number of Bits | 11.4 Bit |
INL - Integral Nonlinearity | 0.4 LSB |
Moisture Sensitive | Yes |
Pd - Power Dissipation | 454 mW |
Product Type | ADCs - Analog to Digital Converters |
SFDR - Spurious Free Dynamic Range | 89 dB |
SINAD - Signal to Noise and Distortion Ratio | 70.3 dB |
Factory Pack Quantity | 250 |
Subcategory | Data Converter ICs |
THD - Total Harmonic Distortion | 78 dB |
Unit Weight | 0.004868 oz |
For more information, please refer to datasheet
Documents
ADC32J25IRGZT Datasheet |
More Information
The ADC32J2x is a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The devices support JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.