ADC32J42IRGZT Texas Instruments - Yeehing Electronics

Dual-Channel, 14-Bit, 50-MSPS Analog-to-Digital Converter (ADC)

Pricing (USD)

Quantity	Unit Price
1 — 99	30.83
100 — 249	27.404
250 — 999	22.528
1,000 +	14.10

The above prices are for reference only.

Specifications

Manufacturer	Texas Instruments
Product Category	Analog to Digital Converters - ADC
RoHS	Y
Series	ADC32J42
Mounting Style	SMD/SMT
Package / Case	VQFN-48
Resolution	14 bit
Number of Channels	2 Channel
Sampling Rate	50 MS/s
Input Type	Differential/Single-Ended
Interface Type	JESD204B
Architecture	Pipeline
Reference Type	External, Internal
Analog Supply Voltage	1.8 V
Digital Supply Voltage	1.8 V
SNR - Signal to Noise Ratio	69.1 dB
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Packaging	Reel
Features	Low Power
Height	1 mm
Length	7.15 mm
Number of Converters	2 Converter
Output Type	CML
Power Consumption	281 mW
Type	High Speed ADC
Width	7.15 mm
Brand	Texas Instruments
Shutdown	No Shutdown
DNL - Differential Nonlinearity	0.3 LSB
ENOB - Effective Number of Bits	11.9 Bit
INL - Integral Nonlinearity	1.5 LSB
Moisture Sensitive	Yes
Pd - Power Dissipation	281 mW
Product Type	ADCs - Analog to Digital Converters
SFDR - Spurious Free Dynamic Range	100 dB
SINAD - Signal to Noise and Distortion Ratio	73.2 dB
Factory Pack Quantity	250
Subcategory	Data Converter ICs
THD - Total Harmonic Distortion	78 dB
Unit Weight	0.004868 oz

For more information, please refer to datasheet

Documents

ADC32J42IRGZT Datasheet

More Information

The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC32J4x family supports JESD204B interface in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock, which is used to serialize the 14-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps.