CD54AC112F3A Texas Instruments - Yeehing Electronics

Dual Negative Edge Triggered J-K Flip-Flops with Set and Reset

Pricing (USD)

Quantity	Unit Price
1 — 99	22.77
100 — 249	19.89
250 — 999	15.336
1,000 +	9.60

The above prices are for reference only.

Specifications

For more information, please refer to datasheet

Documents

CD54AC112F3A Datasheet

More Information

The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.