CD74AC112M Texas Instruments - Yeehing Electronics

Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset

Pricing (USD)

Quantity	Unit Price
1 — 99	0.939
100 — 249	0.722
250 — 999	0.532
1,000 +	0.27

The above prices are for reference only.

Specifications

Manufacturer	Texas Instruments
Product Category	Flip Flops
RoHS	Y
Number of Circuits	2
Logic Family	AC
Logic Type	J-K Negative Edge Triggered Flip-Flop
Polarity	Inverting/Non-Inverting
Input Type	CMOS, LVTTL
Output Type	Differential
Propagation Delay Time	129 ns
High Level Output Current	- 24 mA
Low Level Output Current	24 mA
Supply Voltage - Min	1.5 V
Supply Voltage - Max	5.5 V
Minimum Operating Temperature	- 55 C
Maximum Operating Temperature	+ 125 C
Mounting Style	SMD/SMT
Package / Case	SOP-16
Packaging	Tube
Function	Dual
Height	1.58 mm
Length	9.9 mm
Operating Temperature Range	- 55 C to + 125 C
Quiescent Current	4 uA
Series	CD74AC112
Width	3.91 mm
Brand	Texas Instruments
Number of Channels	2
Number of Input Lines	2
Number of Output Lines	1
Operating Supply Voltage	1.5 V to 5.5 V
Product Type	Flip Flops
Reset Type	Set, Reset
Factory Pack Quantity	40
Subcategory	Logic ICs
Unit Weight	0.004998 oz

For more information, please refer to datasheet

Documents

CD74AC112M Datasheet

More Information

The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.