Description
CD74AC139E Texas Instruments - Yeehing Electronics
Dual 2-to-4 Line Decoder/Demultiplexer
Pricing (USD)
| Quantity | Unit Price |
| 1 — 99 | 0.622 |
| 100 — 249 | 0.479 |
| 250 — 999 | 0.353 |
| 1,000 + | 0.18 |
The above prices are for reference only.
Specifications
| Manufacturer | Texas Instruments |
| Product Category | Encoders, Decoders, Multiplexers & Demultiplexers |
| RoHS | Y |
| Product | Decoders / Demultiplexers |
| Logic Family | AC |
| Number of Input Lines | 2 Input |
| Number of Output Lines | 4 Output |
| Propagation Delay Time | 10.5 ns |
| Supply Voltage - Min | 1.5 V |
| Supply Voltage - Max | 5.5 V |
| Minimum Operating Temperature | - 55 C |
| Maximum Operating Temperature | + 125 C |
| Mounting Style | Through Hole |
| Package / Case | PDIP-16 |
| Packaging | Tube |
| Function | Dual 2 to 4 |
| Height | 4.57 mm |
| Input Voltage | - 0.5 V to 6.0 V |
| Length | 19.3 mm |
| Number of Circuits | Dual |
| Operating Temperature Range | - 55 C to + 125 C |
| Output Current | +/- 50 mA |
| Output Voltage | - 0.5 V to 6 V |
| Series | CD74AC139 |
| Technology | CMOS |
| Width | 6.35 mm |
| Brand | Texas Instruments |
| Logic Type | Decoders/Demultiplexers |
| Supply Current - Max | 0.008 mA |
| High Level Output Current | - 24 mA |
| Low Level Output Current | 24 mA |
| Maximum Clock Frequency | 100 MHz |
| Operating Supply Voltage | 1.5 V to 5.5 V |
| Product Type | Encoders, Decoders, Multiplexers & Demultiplexers |
| Factory Pack Quantity | 25 |
| Subcategory | Logic ICs |
| Unit Weight | 0.033570 oz |
For more information, please refer to datasheet
Documents
| CD74AC139E Datasheet |
More Information
The AC139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 1.5-V to 5.5-V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
