Texas Instruments
CD74AC323M
CD74AC323M
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$0.27 USD
Regular price
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$0.27 USD
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CD74AC323M Texas Instruments - Yeehing Electronics
8-Input Universal Shift/Storage Register with Common Parallel I/O Pins and Synchronous Reset
Pricing (USD)
| Quantity | Unit Price |
| 1 — 99 | 0.944 |
| 100 — 249 | 0.726 |
| 250 — 999 | 0.534 |
| 1,000 + | 0.27 |
The above prices are for reference only.
Specifications
| Manufacturer | Texas Instruments |
| Product Category | Counter Shift Registers |
| RoHS | Y |
| Counting Sequence | Serial/Parallel to Serial/Parallel |
| Number of Circuits | 1 |
| Number of Bits | 8 bit |
| Package / Case | SOIC-20 |
| Logic Family | AC |
| Logic Type | CMOS |
| Number of Input Lines | 10 |
| Output Type | 3-State |
| Propagation Delay Time | 162 ns, 18.1 ns, 12.9 ns |
| Supply Voltage - Min | 1.5 V |
| Supply Voltage - Max | 5.5 V |
| Minimum Operating Temperature | - 55 C |
| Maximum Operating Temperature | + 125 C |
| Packaging | Tube |
| Features | No Parallel Enable Input |
| Function | Shift Register |
| Height | 2.35 mm |
| Length | 12.8 mm |
| Operating Temperature Range | - 55 C to + 125 C |
| Series | CD74AC323 |
| Width | 7.52 mm |
| Brand | Texas Instruments |
| Mounting Style | SMD/SMT |
| Number of Output Lines | 10 |
| Supply Current - Max | 0.008 mA |
| Operating Supply Voltage | 1.8 V, 2, 5 V, 3.3 V, 5 V |
| Product Type | Counter Shift Registers |
| Reset Type | Synchronous |
| Factory Pack Quantity | 25 |
| Subcategory | Logic ICs |
| Triggering Type | Positive Edge |
| Unit Weight | 0.017637 oz |
For more information, please refer to datasheet
Documents
| CD74AC323M Datasheet |
More Information
The RCA CD54/74AC299 and CD54/74AC323 and the CD54/74ACT299 and CD54/74ACT323 are 3-state, 8-input universal shift/storage registers with common parallel I/O pins. These devices use the RCA ADVANCED CMOS technology. These registers have four synchronous-operating modes controlled by the two select inputs as shown in the Mode Select (S0, S1) table. The Mode Select, the Serial Data (DSO, DS7), and the Parallel Data (I/O0 - I/O7) respond only to the LOW-TO-HIGH transition of the clock (CP) pulse. S0, S1 and Data inputs must be present one setup time prior to the positive transition of the clock.
