CD74ACT646M Texas Instruments - Yeehing Electronics

Octal Non-Inverting Bus Transceivers/Registers with 3-State Outputs

Pricing (USD)

Quantity	Unit Price
1 — 99	2.749
100 — 249	2.409
250 — 999	1.689
1,000 +	0.95

The above prices are for reference only.

Specifications

Manufacturer	Texas Instruments
Product Category	Bus Transceivers
RoHS	Y
Logic Family	ACT
Input Level	TTL
Output Level	CMOS
Output Type	3-State
High Level Output Current	- 24 mA
Low Level Output Current	24 mA
Propagation Delay Time	12.5 ns
Supply Voltage - Max	5.5 V
Supply Voltage - Min	4.5 V
Minimum Operating Temperature	- 55 C
Maximum Operating Temperature	+ 125 C
Package / Case	SOIC-24
Packaging	Tube
Function	Bus Transceiver / Register
Height	2.35 mm
Length	15.4 mm
Number of Circuits	8
Operating Temperature Range	- 55 C to + 125 C
Product	Registered Transceiver
Series	CD74ACT646
Technology	CMOS
Width	7.52 mm
Brand	Texas Instruments
Mounting Style	SMD/SMT
Number of Channels	8
Supply Current - Max	8 uA
Operating Supply Voltage	4.5 V to 5.5 V
Pd - Power Dissipation	400 mW
Polarity	Non-Inverting
Product Type	Bus Transceivers
Factory Pack Quantity	25
Subcategory	Logic ICs
Triggering Type	Positive Edge
Unit Weight	0.022025 oz

For more information, please refer to datasheet

Documents

CD74ACT646M Datasheet

More Information

The RCA CD54/74AC646 and CD54/74AC648 and the CD54/74ACT646 and CD54/74ACT648 3-state, octal-bus transceiver/registers use the RCA ADVANCED CMOS technology. The CD54/74AC648 and CD54/74ACT648 have inverting outputs. The CD54/74AC646 and CD54/74ACT646 have non-inverting outputs. These devices are bus transceivers with D-type flip-flops which act as internal storage registers on the LOW-to-HIGH transition of either CAB or CBA clock inputs. Output Enable (OE) and Direction (DIR) inputs control the transceiver functions. Data present at the high-impedance output can be stored in either register or both but only one of the two buses can be enabled as outputs at any one time. The Select controls (SAB and SBA) can multiplex stored and transparent (real time) data. The Direction control determines which data bus will receive data when the Output Enable (OE) is LOW. In the high-impednace mode (Output Enable HIGH), A data can be stored in one register and B data can be stored in the other register. The clocks are not gated with the Direction (DIR) and Output Enable (OE) terminals; data at the A or B terminals can be clocked into the storage flip-flops at any time.