CDC509PWR Texas Instruments - Yeehing Electronics

3.3-V phase lock loop clock driver

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Specifications

For more information, please refer to datasheet

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More Information

The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCC and is designed to drive up to five clock loads per output.