Description
CDCF5801ADBQ Texas Instruments - Yeehing Electronics
Low-jitter PLL-based multiplier & divider with programmable delay lines down to sub 10 ps
Pricing (USD)
| Quantity | Unit Price |
| 1 — 99 | 5.732 |
| 100 — 249 | 4.673 |
| 250 — 999 | 3.673 |
| 1,000 + | 2.18 |
The above prices are for reference only.
Specifications
| Manufacturer | Texas Instruments |
| Product Category | Phase Locked Loops - PLL |
| RoHS | Y |
| Type | Zero Delay PLL Clock Multiplier |
| Number of Circuits | 1 |
| Maximum Input Frequency | 240 MHz |
| Minimum Input Frequency | 12.5 MHz |
| Output Frequency Range | 280 MHz |
| Supply Voltage - Max | 3.6 V |
| Supply Voltage - Min | 3 V |
| Minimum Operating Temperature | - 40 C |
| Maximum Operating Temperature | + 85 C |
| Mounting Style | SMD/SMT |
| Package / Case | QSOP-24 |
| Packaging | Tube |
| Features | 3.3V Vcc/Vdd, Spread Spectrum Clocking (SSC) |
| Height | 1.5 mm |
| Length | 8.75 mm |
| Series | CDCF5801A |
| Width | 4 mm |
| Brand | Texas Instruments |
| Input Level | HSTL, LVPECL, LVTTL |
| Output Level | LVDS, LVPECL, LVTTL |
| Moisture Sensitive | Yes |
| Operating Supply Voltage | 3.3 V |
| Product Type | PLLs - Phase Locked Loops |
| Factory Pack Quantity | 50 |
| Subcategory | Wireless & RF Integrated Circuits |
| Unit Weight | 0.059966 oz |
For more information, please refer to datasheet
Documents
| CDCF5801ADBQ Datasheet |
More Information
The CDCF5801A provides clock multiplication from a reference clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input detects a low signal at the time of the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition. This unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin, while strapping the LEADLAG pin to dc high or low. Further possible applications are:
