CDCLVD1204RGTT Texas Instruments - Yeehing Electronics

Low jitter, 2-input selectable 1:4 universal-to-LVDS buffer

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Specifications

For more information, please refer to datasheet

Documents

More Information

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.