Description
CDCLVP111HFG/EM Texas Instruments - Yeehing Electronics
1:10 high speed clock buffer with selectable input clock driver
Pricing (USD)
Quantity | Unit Price |
1 — 99 | 1357.268 |
100 — 249 | 1284.557 |
250 — 999 | 1211.846 |
1,000 + | 950.09 |
The above prices are for reference only.
Specifications
For more information, please refer to datasheet
Documents
CDCLVP111HFG/EM Datasheet |
More Information
The CDCLVP111-SP clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111-SP can accept two clock sources into an input multiplexer. The CDCLVP111-SP is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.