CDCU877RHAT Texas Instruments - Yeehing Electronics

1.8-V phase-lock loop clock driver for DDR2 SDRAM applications

Pricing (USD)

Quantity	Unit Price
1 — 99	8.9
100 — 249	7.256
250 — 999	5.703
1,000 +	3.39

The above prices are for reference only.

Specifications

Manufacturer	Texas Instruments
Product Category	Clock Drivers & Distribution
RoHS	Y
Series	CDCU877
Output Type	SSTL-18
Max Output Freq	400 MHz
Supply Voltage - Max	1.9 V
Supply Voltage - Min	1.7 V
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	VQFN-40
Packaging	Reel
Input Type	SSTL-18
Number of Outputs	40
Type	Phase-Locked-Loops (PLLs) and Oscillators
Brand	Texas Instruments
Maximum Input Frequency	400 MHz
Moisture Sensitive	Yes
Operating Supply Current	135 mA
Product Type	Clock Drivers & Distribution
Factory Pack Quantity	250
Subcategory	Clock & Timer ICs
Unit Weight	0.003668 oz

For more information, please refer to datasheet

Documents

CDCU877RHAT Datasheet

More Information

The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.