Description
CDCUN1208LPRHBT Texas Instruments - Yeehing Electronics
Ultra-low power, 2:8 fan-out buffer with universal inputs and outputs
Pricing (USD)
Quantity | Unit Price |
1 — 99 | 9.203 |
100 — 249 | 8.039 |
250 — 999 | 6.198 |
1,000 + | 3.88 |
The above prices are for reference only.
Specifications
Manufacturer | Texas Instruments |
Product Category | Clock Drivers & Distribution |
RoHS | Y |
Series | CDCUN1208LP |
Multiply / Divide Factor | 2 |
Output Type | HCSL, LVDS, LVCMOS |
Max Output Freq | 400 MHz |
Supply Voltage - Max | 3.6 V |
Supply Voltage - Min | 1.7 V |
Minimum Operating Temperature | - 40 C |
Maximum Operating Temperature | + 85 C |
Mounting Style | SMD/SMT |
Package / Case | VQFN-32 |
Packaging | Reel |
Number of Outputs | 8 |
Type | Fanout Buffers |
Brand | Texas Instruments |
Moisture Sensitive | Yes |
Operating Supply Current | 4 mA |
Product Type | Clock Drivers & Distribution |
Factory Pack Quantity | 250 |
Subcategory | Clock & Timer ICs |
Unit Weight | 0.002547 oz |
For more information, please refer to datasheet
Documents
CDCUN1208LPRHBT Datasheet |
More Information
The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge-rate control. The clock buffer supports PCIe Gen1, Gen2 and Gen3. One of the device inputs includes a divider that provides divide values of /1, /2, /4, or /8. The CDCUN1208LP is offered in a 32-pin QFN package, reducing the solution footprint. The device is flexible and easy to use. The state of certain pins determines device configuration at power up. Alternately, the CDCUN1208LP provides a SPI/I2C port with which a host processor controls device settings. The CDCUN1208LP delivers excellent additive jitter performance, and low power consumption. The output section includes four dedicated supply pins enabling the operation of output ports from different power supply domains. This provides the ability to clock devices switching at different LVCMOS levels without the need for external logic level translation circuitry.