Description
CDCVF310PWR Texas Instruments - Yeehing Electronics
High performance 1:10 clock buffer for general purpose applications with support up to 85C
Pricing (USD)
Quantity | Unit Price |
1 — 99 | 3.279 |
100 — 249 | 2.673 |
250 — 999 | 2.101 |
1,000 + | 1.25 |
The above prices are for reference only.
Specifications
Manufacturer | Texas Instruments |
Product Category | Clock Buffer |
RoHS | Y |
Series | CDCVF310 |
Number of Outputs | 10 Output |
Maximum Input Frequency | 200 MHz |
Propagation Delay - Max | 4 ns |
Supply Voltage - Max | 3.6 V |
Supply Voltage - Min | 2.3 V |
Minimum Operating Temperature | - 40 C |
Maximum Operating Temperature | + 85 C |
Mounting Style | SMD/SMT |
Package / Case | TSSOP-24 |
Packaging | Reel |
Height | 1.15 mm |
Input Type | LVTTL |
Length | 7.8 mm |
Output Type | LVTTL |
Width | 4.4 mm |
Brand | Texas Instruments |
Max Output Freq | 200 MHz |
Product Type | Clock Buffer |
Factory Pack Quantity | 2000 |
Subcategory | Clock & Timer ICs |
Unit Weight | 0.003157 oz |
For more information, please refer to datasheet
Documents
CDCVF310PWR Datasheet |
More Information
The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.