DS90UB902QSQ/NOPB Texas Instruments - Yeehing Electronics

10 - 43MHz 14 Bit Color FPD-Link III Deserializer with Bidirectional Control Channel

Pricing (USD)

Quantity	Unit Price
1 — 99	8.111
100 — 249	6.612
250 — 999	5.197
1,000 +	3.09

The above prices are for reference only.

Specifications

Manufacturer	Texas Instruments
Product Category	Display Interface IC
RoHS	Y
Mounting Style	SMD/SMT
Package / Case	WQFN-40
Series	DS90UB902Q-Q1
Type	Display Interface
Maximum Operating Frequency	43 MHz
Operating Supply Voltage	1.71 V to 1.89 V
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 105 C
Packaging	Reel
Description/Function	14 Bit Color FPD-Link III Deserializer with Bidirectional Control Channel
Features	BIST
Output Type	LVCMOS
Brand	Texas Instruments
Interface Type	I2C
Moisture Sensitive	Yes
Product Type	Display Interface IC
Factory Pack Quantity	1000
Subcategory	Interface ICs
Unit Weight	0.001929 oz

For more information, please refer to datasheet

Documents

DS90UB902QSQ/NOPB Datasheet

More Information

The DS90UB901Q/DS90UB902Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bidirectional control channel transport that supports I2C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.