JM38510/34102BEA Texas Instruments - Yeehing Electronics

Dual J-K Positive-Edge-Triggered Flip-Flops W/Clear And Preset

Pricing (USD)

Quantity	Unit Price
1 — 99	13.076
100 — 249	11.422
250 — 999	8.806
1,000 +	5.51

The above prices are for reference only.

Specifications

For more information, please refer to datasheet

Documents

JM38510/34102BEA Datasheet

More Information

These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and trying J high. They also can perform as D-type flip-flops if J and K are tied together.