LMH0031VS/NOPB Texas Instruments - Yeehing Electronics

Digital Video Deserializer/Descrambler w/ Video & Ancillary Data FIFOs

Pricing (USD)

Quantity	Unit Price
1 — 99	31.72
100 — 249	28.196
250 — 999	23.178
1,000 +	14.51

The above prices are for reference only.

Specifications

Manufacturer	Texas Instruments
Product Category	Serializers & Deserializers - Serdes
RoHS	Y
Type	Deserializer
Data Rate	1.485 Gb/s
Input Type	ECL/LVDS
Output Type	LVCMOS
Number of Inputs	1 Input
Number of Outputs	20 Output
Operating Supply Voltage	2.375 V to 2.625 V
Minimum Operating Temperature	0 C
Maximum Operating Temperature	+ 70 C
Mounting Style	SMD/SMT
Package / Case	TQFP-64
Packaging	Tray
Series	LMH0031
Brand	Texas Instruments
Moisture Sensitive	Yes
Product Type	Serializers & Deserializers - Serdes
Factory Pack Quantity	160
Subcategory	Interface ICs
Supply Voltage - Max	3.45 V
Supply Voltage - Min	3.15 V
Unit Weight	0.012720 oz

For more information, please refer to datasheet

Documents

LMH0031VS/NOPB Datasheet

More Information

The LMH0031 SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate clock. It also deserializes and decodes SMPTE 259M, 270Mbps, 360Mbps and SMPTE 344M (proposed) 540Mbps serial component video data, to 10-bit parallel data. Functions performed by the LMH0031 include: clock/data recovery from the serial data, serial-to-parallel data conversion, SMPTE standard data decoding, NRZI-to-NRZ conversion, parallel data clock generation, word framing, CRC and EDH data checking and handling, Ancillary Data extraction and automatic video format determination. The parallel video output features a variable-depth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented.