LMK1D1204RGTR Texas Instruments - Yeehing Electronics

4-channel output LVDS 1.8-V buffer

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Specifications

For more information, please refer to datasheet

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More Information

The LMK1D120x clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 or 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The LMK1D12x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML or LVCMOS.