Description
LP38853SX-ADJ/NOPB Texas Instruments - Yeehing Electronics
3-A, low-VIN (1.04-V), adjustable ultra-low-dropout voltage regulator with enable
Pricing (USD)
Quantity | Unit Price |
1 — 99 | 3.666 |
100 — 249 | 3.213 |
250 — 999 | 2.252 |
1,000 + | 1.27 |
The above prices are for reference only.
Specifications
Manufacturer | Texas Instruments |
Product Category | LDO Voltage Regulators |
RoHS | Y |
Mounting Style | SMD/SMT |
Package / Case | TO-263-7 |
Output Voltage | 0.8 V to 1.8 V |
Output Current | 3 A |
Number of Outputs | 1 Output |
Polarity | Positive |
Quiescent Current | 8.5 mA |
Input Voltage MAX | 5.5 V |
Input Voltage MIN | 3 V |
Output Type | Adjustable |
Minimum Operating Temperature | - 40 C |
Maximum Operating Temperature | + 125 C |
Dropout Voltage | 240 mV |
Series | LP38853 |
Packaging | Reel |
Operating Temperature Range | - 40 C to + 125 C |
Product | Linear Voltage Regulators |
Type | Linear Regulator |
Brand | Texas Instruments |
Dropout Voltage - Max | 0.3 V at 3 A |
PSRR / Ripple Rejection - Typ | 80 dB |
Voltage Regulation Accuracy | +/- 1.5 % |
Development Kit | LP38853EVAL |
Ib - Input Bias Current | 7 mA |
Line Regulation | 0.1 %/V |
Load Regulation | 0.2 %/A |
Moisture Sensitive | Yes |
Operating Supply Current | 10 mA |
Pd - Power Dissipation | Internally Limited |
Product Type | LDO Voltage Regulators |
Factory Pack Quantity | 500 |
Subcategory | PMIC - Power Management ICs |
Unit Weight | 0.056438 oz |
For more information, please refer to datasheet
Documents
LP38853SX-ADJ/NOPB Datasheet |
More Information
The LP38853 is a high-current, fast-response regulator that can maintain output voltage regulation with extremely low input-to-output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: VBIAS provides voltage to drive the gate of the NMOS power transistor; VIN is the input voltage which supplies power to the load. The use of an external bias rail allows the device to operate from ultra-low VIN voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an NMOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability.