OPA2192QDGKRQ1


YeeHing #: Y001-OPA2192QDGKRQ1
Inventory: 3800

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Description

OPA2192QDGKRQ1 Texas Instruments - Yeehing Electronics

Automotive 36-V, Precision, RRIO, Low Offset Voltage, Low Input Bias Current Op Amp With e-trim

Pricing (USD)

Quantity Unit Price
1 — 99 4.038
100 — 249 3.538
250 — 999 2.481
1,000 + 1.40

The above prices are for reference only.

Specifications

Manufacturer Texas Instruments
Product Category Operational Amplifiers - Op Amps
RoHS Y
Mounting Style SMD/SMT
Package / Case VSSOP-8
Supply Voltage - Max 36 V
Output Current per Channel 65 mA
Number of Channels 1 Channel
GBP - Gain Bandwidth Product 10 MHz
SR - Slew Rate 20 V/us
CMRR - Common Mode Rejection Ratio 100 dB to 120 dB
Ib - Input Bias Current 5 pA
Vos - Input Offset Voltage 0.025 mV
Supply Voltage - Min 4.5 V
Minimum Operating Temperature - 40 C
Maximum Operating Temperature + 125 C
Shutdown No Shutdown
Series OPA2192-Q1
Qualification AEC-Q100
Packaging Reel
Amplifier Type Low Offset Voltage, Low Input Bias Current Amplifier
Features EMI Hardened, High Cload Drive
Input Type Rail-to-Rail
Output Type Rail-to-Rail
Product Operational Amplifiers
Brand Texas Instruments
THD plus Noise 0.00008 %
Development Kit DIP-ADAPTER-EVM, DIYAMP-EVM, OPAMPEVM
en - Input Voltage Noise Density 5.5 nV/sqrt Hz
In - Input Noise Current Density 1.5 fA/sqrt Hz
Maximum Dual Supply Voltage 18 V
Minimum Dual Supply Voltage 2.25 V
Moisture Sensitive Yes
Product Type Op Amps - Operational Amplifiers
PSRR - Power Supply Rejection Ratio 1 uV/V
Factory Pack Quantity 2500
Subcategory Amplifier ICs
Vcm - Common Mode Voltage Negative Rail - 0.1 V to Positive Rail + 0.1 V
Unit Weight 0.001034 oz

For more information, please refer to datasheet

Documents

OPA2192QDGKRQ1 Datasheet

More Information

The OPAx192-Q1 family (OPA192-Q1 and OPA2192-Q1) is a new generation of 36-V, e-trim operational amplifiers. The OPAx192-Q1 family of operational amplifiers use e-trim, a method of package-level trim for offset and offset temperature drift implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package molding.

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