Description
OPA2197QDGKRQ1 Texas Instruments - Yeehing Electronics
Dual automotive 36-V, precision, rail-to-rail input output, low offset voltage op amp
Pricing (USD)
| Quantity | Unit Price |
| 1 — 99 | 2.077 |
| 100 — 249 | 1.82 |
| 250 — 999 | 1.276 |
| 1,000 + | 0.72 |
The above prices are for reference only.
Specifications
| Manufacturer | Texas Instruments |
| Product Category | Operational Amplifiers - Op Amps |
| RoHS | Y |
| Mounting Style | SMD/SMT |
| Package / Case | VSSOP-8 |
| Supply Voltage - Max | 36 V |
| Output Current per Channel | 65 mA |
| Number of Channels | 2 Channel |
| GBP - Gain Bandwidth Product | 10 MHz |
| SR - Slew Rate | 20 V/us |
| CMRR - Common Mode Rejection Ratio | 120 dB to 140 dB |
| Ib - Input Bias Current | 20 pA |
| Vos - Input Offset Voltage | 0.25 mV |
| Supply Voltage - Min | 4.5 V |
| Operating Supply Current | 1 mA |
| Minimum Operating Temperature | - 40 C |
| Maximum Operating Temperature | + 125 C |
| Shutdown | No Shutdown |
| Series | OPA2197-Q1 |
| Packaging | Reel |
| Amplifier Type | Precision Operational Amplifier |
| Features | EMI Hardened, High Cload Drive |
| Input Type | Rail-to-Rail |
| Output Type | Rail-to-Rail |
| Product | Operational Amplifiers |
| Brand | Texas Instruments |
| THD plus Noise | 0.00008 % |
| 3 dB Bandwidth | - |
| en - Input Voltage Noise Density | 5.5 nV/sqrt Hz |
| In - Input Noise Current Density | 1.5 fA/sqrt Hz |
| Ios - Input Offset Current | 20 pA |
| Maximum Dual Supply Voltage | +/- 18 V |
| Minimum Dual Supply Voltage | +/- 2.25 V |
| Moisture Sensitive | Yes |
| Product Type | Op Amps - Operational Amplifiers |
| Factory Pack Quantity | 2500 |
| Subcategory | Amplifier ICs |
| Unit Weight | 0.001034 oz |
For more information, please refer to datasheet
Documents
| OPA2197QDGKRQ1 Datasheet |
More Information
The OPAx197-Q1 family (OPA197-Q1, OPA2197-Q1, and OPA4197-Q1) is part of a new generation of 36-V, e-trim™ operational amplifiers. The OPAx197-Q1 family of e-trim operational amplifiers uses a proprietary method of package-level trim for offset and offset temperature drift implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package molding.
