SN65DSI85ZXHR Texas Instruments - Yeehing Electronics

Dual-channel MIPI® DSI to dual-link Flatlink™ LVDS bridge

Pricing (USD)

The above prices are for reference only.

Specifications

For more information, please refer to datasheet

Documents

More Information

The SN65DSI85 DSI to FlatLink bridge features a dual-channel MIPI D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS, or two Single-Link LVDS interface(s) with four data lanes per link.