Texas Instruments
SN74ABT16833DLR
SN74ABT16833DLR
Regular price
$0.80 USD
Regular price
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$0.80 USD
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SN74ABT16833DLR Texas Instruments - Yeehing Electronics
Dual 8-Bit To 9-Bit Parity Bus Transceivers
Pricing (USD)
| Quantity | Unit Price |
| 1 — 99 | 2.305 |
| 100 — 249 | 2.02 |
| 250 — 999 | 1.416 |
| 1,000 + | 0.80 |
The above prices are for reference only.
Specifications
| Manufacturer | Texas Instruments |
| Product Category | Bus Transceivers |
| RoHS | Y |
| Logic Family | ABT |
| Input Level | TTL |
| Output Level | TTL |
| Output Type | 3-State |
| High Level Output Current | - 32 mA |
| Low Level Output Current | 64 mA |
| Propagation Delay Time | 4.3 ns |
| Supply Voltage - Max | 5.5 V |
| Supply Voltage - Min | 4.5 V |
| Minimum Operating Temperature | - 40 C |
| Maximum Operating Temperature | + 85 C |
| Package / Case | SSOP-56 |
| Packaging | Reel |
| Function | Registered Transceiver with Parity Checker |
| Height | 2.59 mm |
| Length | 18.41 mm |
| Number of Circuits | 2 |
| Operating Temperature Range | - 40 C to + 85 C |
| Product | Parity Transceiver |
| Quiescent Current | 28 mA |
| Series | SN74ABT16833 |
| Technology | BiCMOS |
| Width | 7.49 mm |
| Brand | Texas Instruments |
| Mounting Style | SMD/SMT |
| Number of Channels | 16 |
| Supply Current - Max | 36 mA |
| Operating Supply Voltage | 5 V |
| Polarity | Non-Inverting |
| Product Type | Bus Transceivers |
| Factory Pack Quantity | 1000 |
| Subcategory | Logic ICs |
| Triggering Type | Positive Edge |
| Unit Weight | 0.024339 oz |
For more information, please refer to datasheet
Documents
| SN74ABT16833DLR Datasheet |
More Information
The 'ABT16833 consist of two noninverting 8-bit to 9-bit parity bus transceivers and are designed for communication between data buses. For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin (1PARITY or 2PARITY). When data is transmitted from the B bus to the A bus, 1PARITY (or 2PARITY) is configured as an input and combined with the B-input data to generate an active-low error flag if odd parity is not detected.
