Description
SN74AHCT138MDREP Texas Instruments - Yeehing Electronics
Enhanced Product 3-line to 8-line decoder / demultiplexer
Pricing (USD)
Quantity | Unit Price |
1 — 99 | 1.456 |
100 — 249 | 1.203 |
250 — 999 | 0.864 |
1,000 + | 0.45 |
The above prices are for reference only.
Specifications
Manufacturer | Texas Instruments |
Product Category | Encoders, Decoders, Multiplexers & Demultiplexers |
RoHS | Y |
Product | Decoders / Demultiplexers |
Logic Family | AHCT |
Number of Input Lines | 3 Input |
Number of Output Lines | 8 Output |
Propagation Delay Time | 12 ns |
Supply Voltage - Min | 4.5 V |
Supply Voltage - Max | 5.5 V |
Minimum Operating Temperature | - 55 C |
Maximum Operating Temperature | + 125 C |
Mounting Style | SMD/SMT |
Package / Case | SOP-16 |
Packaging | Reel |
Function | Decoder/Demultiplexer |
Height | 1.58 mm |
Length | 9.9 mm |
Number of Circuits | 1 Circuit |
Operating Temperature Range | - 55 C to + 125 C |
Series | SN74AHCT138-EP |
Technology | CMOS |
Width | 3.91 mm |
Brand | Texas Instruments |
Logic Type | Decoders/Demultiplexers |
Supply Current - Max | 0.004 mA |
High Level Output Current | - 8 mA |
Low Level Output Current | 8 mA |
Maximum Clock Frequency | 70 MHz |
Operating Supply Voltage | 5 V |
Product Type | Encoders, Decoders, Multiplexers & Demultiplexers |
Factory Pack Quantity | 2500 |
Subcategory | Logic ICs |
Part # Aliases | V62/03655-01YE |
Unit Weight | 0.004998 oz |
For more information, please refer to datasheet
Documents
SN74AHCT138MDREP Datasheet |
More Information
The SN74AHCT138 3-line to 8-line decoder/demultiplexer is designed to be used in high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.