SN74ALS109ANSR Texas Instruments - Yeehing Electronics

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset

Pricing (USD)

Quantity	Unit Price
1 — 99	1.243
100 — 249	1.027
250 — 999	0.738
1,000 +	0.39

The above prices are for reference only.

Specifications

Manufacturer	Texas Instruments
Product Category	Flip Flops
RoHS	Y
Number of Circuits	2
Logic Family	ALS
Logic Type	J-K Type Flip-Flop
Polarity	Inverting/Non-Inverting
Input Type	TTL
Output Type	TTL
Propagation Delay Time	18 ns
High Level Output Current	- 0.4 mA
Low Level Output Current	8 mA
Supply Voltage - Min	4.5 V
Supply Voltage - Max	5.5 V
Minimum Operating Temperature	0 C
Maximum Operating Temperature	+ 70 C
Mounting Style	SMD/SMT
Package / Case	SO-16
Packaging	Reel
Function	J-K Type
Height	1.95 mm
Length	10.3 mm
Operating Temperature Range	0 C to + 70 C
Series	SN74ALS109A
Width	5.3 mm
Brand	Texas Instruments
Number of Channels	2
Number of Input Lines	5
Number of Output Lines	2
Operating Supply Voltage	4.5 V to 5.5 V
Product Type	Flip Flops
Reset Type	Set, Reset
Factory Pack Quantity	2000
Subcategory	Logic ICs
Unit Weight	0.007079 oz

For more information, please refer to datasheet

Documents

SN74ALS109ANSR Datasheet

More Information

These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.