SN74F109D Texas Instruments - Yeehing Electronics

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset

Pricing (USD)

Quantity	Unit Price
1 — 99	0.669
100 — 249	0.515
250 — 999	0.379
1,000 +	0.19

The above prices are for reference only.

Specifications

Manufacturer	Texas Instruments
Product Category	Flip Flops
RoHS	Y
Number of Circuits	2
Logic Family	F
Logic Type	J-K Type Flip-Flop
Polarity	Inverting/Non-Inverting
Input Type	TTL
Output Type	TTL
Propagation Delay Time	8 ns
High Level Output Current	- 1 mA
Low Level Output Current	20 mA
Supply Voltage - Min	4.5 V
Supply Voltage - Max	5.5 V
Minimum Operating Temperature	0 C
Maximum Operating Temperature	+ 70 C
Mounting Style	SMD/SMT
Package / Case	SOP-16
Packaging	Reel
Function	J-K Type
Height	1.58 mm
Length	9.9 mm
Operating Temperature Range	0 C to + 70 C
Series	SN74F109
Width	3.91 mm
Brand	Texas Instruments
Number of Channels	2
Number of Input Lines	2
Number of Output Lines	1
Operating Supply Voltage	4.5 V to 5.5 V
Product Type	Flip Flops
Reset Type	Set, Reset
Factory Pack Quantity	2500
Subcategory	Logic ICs
Unit Weight	0.004998 oz

For more information, please refer to datasheet

Documents

SN74F109D Datasheet

More Information

These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and trying J high. They also can perform as D-type flip-flops if J and K are tied together.