SN74F112N Texas Instruments - Yeehing Electronics

Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset

Pricing (USD)

Quantity	Unit Price
1 — 99	0.63
100 — 249	0.485
250 — 999	0.357
1,000 +	0.18

The above prices are for reference only.

Specifications

Manufacturer	Texas Instruments
Product Category	Flip Flops
RoHS	Y
Number of Circuits	2
Logic Family	F
Logic Type	J-K Type Flip-Flop
Polarity	Inverting/Non-Inverting
Input Type	TTL
Output Type	TTL
Propagation Delay Time	6.5 ns
High Level Output Current	- 1 mA
Low Level Output Current	20 mA
Supply Voltage - Min	4.5 V
Supply Voltage - Max	5.5 V
Minimum Operating Temperature	0 C
Maximum Operating Temperature	+ 70 C
Mounting Style	Through Hole
Package / Case	PDIP-16
Packaging	Tube
Function	Dual Negative Edge Triggered
Height	4.57 mm
Length	19.3 mm
Operating Temperature Range	0 C to + 70 C
Series	SN74F112
Width	6.35 mm
Brand	Texas Instruments
Number of Channels	2
Number of Input Lines	2
Number of Output Lines	1
Operating Supply Voltage	4.5 V to 5.5 V
Product Type	Flip Flops
Reset Type	Set, Reset
Factory Pack Quantity	25
Subcategory	Logic ICs
Unit Weight	0.033570 oz

For more information, please refer to datasheet

Documents

SN74F112N Datasheet

More Information

The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high.