Description
SN74GTLP2033DGGR Texas Instruments - Yeehing Electronics
8-Bit LVTTL-GTLP Adjustable-Edge-Rate Registered Transceiver with Split LVTTL Port and Feedback Path
Pricing (USD)
Quantity | Unit Price |
1 — 99 | 6.285 |
100 — 249 | 5.124 |
250 — 999 | 4.027 |
1,000 + | 2.39 |
The above prices are for reference only.
Specifications
Manufacturer | Texas Instruments |
Product Category | Translation - Voltage Levels |
RoHS | Y |
Propagation Delay Time | 8.8 ns |
Supply Voltage - Max | 3.45 V |
Supply Voltage - Min | 3.15 V |
Minimum Operating Temperature | - 40 C |
Maximum Operating Temperature | + 85 C |
Mounting Style | SMD/SMT |
Package / Case | TSSOP-48 |
Packaging | Reel |
Features | Partial power down (Ioff), Over-voltage tolerant inputs, Power up 3 state, Bias Vcc, Variable outpu |
Operating Temperature Range | - 40 C to + 85 C |
Output Type | 3-State or Open Drain |
Series | SN74GTLP2033 |
Brand | Texas Instruments |
Logic Family | GTLP |
Logic Type | CMOS |
High Level Output Current | - 24 mA |
Low Level Output Current | 100 mA |
Operating Supply Current | 40 mA |
Product Type | Translation - Voltage Levels |
Factory Pack Quantity | 2000 |
Subcategory | Logic ICs |
Unit Weight | 0.007873 oz |
For more information, please refer to datasheet
Documents
SN74GTLP2033DGGR Datasheet |
More Information
The SN74GTLP2033 is a high-drive, 8-bit, three-wire registered transceiver that provides inverted LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and flip-flop modes of data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and diagnostics monitoring, the same functionality as the SN74FB2033. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11 .