Description
SN74HC166AIDRQ1 Texas Instruments - Yeehing Electronics
Automotive Catalog 8-Bit Parallel-Load Shift Registers
Pricing (USD)
Quantity | Unit Price |
1 — 99 | 0.595 |
100 — 249 | 0.458 |
250 — 999 | 0.337 |
1,000 + | 0.17 |
The above prices are for reference only.
Specifications
Manufacturer | Texas Instruments |
Product Category | Counter Shift Registers |
RoHS | Y |
Counting Sequence | Serial/Parallel to Serial |
Number of Circuits | 1 |
Number of Bits | 8 bit |
Package / Case | SOP-16 |
Logic Family | 74HC |
Logic Type | CMOS |
Number of Input Lines | 5 |
Output Type | Parallel / Serial |
Propagation Delay Time | 150 ns, 30 ns, 26 ns |
Supply Voltage - Max | 6 V |
Minimum Operating Temperature | - 40 C |
Maximum Operating Temperature | + 125 C |
Qualification | AEC-Q100 |
Packaging | Reel |
Function | Shift Register |
Operating Temperature Range | - 40 C to + 125 C |
Series | SN74HC166A-Q1 |
Width | 3.91 mm |
Brand | Texas Instruments |
Mounting Style | SMD/SMT |
Number of Output Lines | 3 |
Operating Supply Voltage | 2 V to 6 V |
Product Type | Counter Shift Registers |
Factory Pack Quantity | 2500 |
Subcategory | Logic ICs |
Unit Weight | 0.004998 oz |
For more information, please refer to datasheet
Documents
SN74HC166AIDRQ1 Datasheet |
More Information
This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.