SN74LS112AD Texas Instruments - Yeehing Electronics

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset

Pricing (USD)

Quantity	Unit Price
1 — 99	0.598
100 — 249	0.46
250 — 999	0.339
1,000 +	0.17

The above prices are for reference only.

Specifications

Manufacturer	Texas Instruments
Product Category	Flip Flops
RoHS	Y
Number of Circuits	2
Logic Family	LS
Logic Type	J-K Type Flip-Flop
Polarity	Inverting/Non-Inverting
Input Type	TTL
Output Type	TTL
Propagation Delay Time	20 ns
High Level Output Current	- 0.4 mA
Low Level Output Current	8 mA
Supply Voltage - Min	4.75 V
Supply Voltage - Max	5.25 V
Minimum Operating Temperature	0 C
Maximum Operating Temperature	+ 70 C
Mounting Style	SMD/SMT
Package / Case	SOP-16
Packaging	Tube
Function	JK Type
Height	1.58 mm
Length	9.9 mm
Operating Temperature Range	0 C to + 70 C
Series	SN74LS112A
Width	3.91 mm
Brand	Texas Instruments
Number of Channels	2
Number of Input Lines	5
Number of Output Lines	2
Operating Supply Voltage	4.75 V to 5.25 V
Product Type	Flip Flops
Reset Type	Set, Reset
Factory Pack Quantity	40
Subcategory	Logic ICs
Unit Weight	0.004998 oz

For more information, please refer to datasheet

Documents

SN74LS112AD Datasheet

More Information

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.