SN74LS112ANSR Texas Instruments - Yeehing Electronics

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset

Pricing (USD)

Quantity	Unit Price
1 — 99	0.625
100 — 249	0.481
250 — 999	0.354
1,000 +	0.18

The above prices are for reference only.

Specifications

Manufacturer	Texas Instruments
Minimum Operating Temperature	0
Maximum Operating Temperature	70
Factory Pack Quantity	2,000
Package | Pins	SOP (NS) | 16

For more information, please refer to datasheet

Documents

SN74LS112ANSR Datasheet

More Information

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.