Texas Instruments
SN74LS74AN
SN74LS74AN
Regular price
$0.14 USD
Regular price
Sale price
$0.14 USD
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SN74LS74AN Texas Instruments - Yeehing Electronics
Dual D-type pos.-edge-triggered flip-flops with preset and clear
Pricing (USD)
| Quantity | Unit Price |
| 1 — 99 | 0.494 |
| 100 — 249 | 0.38 |
| 250 — 999 | 0.28 |
| 1,000 + | 0.14 |
The above prices are for reference only.
Specifications
| Manufacturer | Texas Instruments |
| Product Category | Flip Flops |
| RoHS | Y |
| Number of Circuits | 2 |
| Logic Family | LS |
| Logic Type | D-Type Latch and Flip-Flop |
| Polarity | Inverting/Non-Inverting |
| Input Type | TTL |
| Output Type | TTL |
| Propagation Delay Time | 40 ns |
| High Level Output Current | - 0.4 mA |
| Low Level Output Current | 8 mA |
| Supply Voltage - Min | 4.75 V |
| Supply Voltage - Max | 5.25 V |
| Minimum Operating Temperature | 0 C |
| Maximum Operating Temperature | + 70 C |
| Mounting Style | SMD/SMT |
| Package / Case | PDIP-14 |
| Packaging | Tube |
| Function | Contain 2 Independent Positive Edge Triggered Flip Flops |
| Height | 4.57 mm |
| Length | 19.3 mm |
| Operating Temperature Range | 0 C to + 70 C |
| Series | SN74LS74A |
| Width | 6.35 mm |
| Brand | Texas Instruments |
| Number of Channels | 2 |
| Number of Input Lines | 3 |
| Number of Output Lines | 1 |
| Operating Supply Voltage | 5 V |
| Product Type | Flip Flops |
| Reset Type | Set, Reset |
| Factory Pack Quantity | 25 |
| Subcategory | Logic ICs |
| Unit Weight | 0.032734 oz |
For more information, please refer to datasheet
Documents
| SN74LS74AN Datasheet |
More Information
These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.
