Texas Instruments
SN74LVC138ADR
SN74LVC138ADR
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$0.05 USD
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SN74LVC138ADR Texas Instruments - Yeehing Electronics
3-Line To 8-Line decoder/Demultiplexer
Pricing (USD)
| Quantity | Unit Price |
| 1 — 99 | 0.235 |
| 100 — 249 | 0.16 |
| 250 — 999 | 0.123 |
| 1,000 + | 0.05 |
The above prices are for reference only.
Specifications
| Manufacturer | Texas Instruments |
| Product Category | Encoders, Decoders, Multiplexers & Demultiplexers |
| RoHS | Y |
| Product | Decoders / Demultiplexers |
| Logic Family | LVC |
| Number of Input Lines | 3 Input |
| Number of Output Lines | 8 Output |
| Propagation Delay Time | 6.7 ns |
| Supply Voltage - Min | 1.65 V |
| Supply Voltage - Max | 3.6 V |
| Minimum Operating Temperature | - 40 C |
| Maximum Operating Temperature | + 85 C |
| Mounting Style | SMD/SMT |
| Package / Case | SOP-16 |
| Packaging | Reel |
| Function | Decoder/Demultiplexer |
| Height | 1.58 mm |
| Length | 9.9 mm |
| Number of Circuits | Triple |
| Operating Temperature Range | - 40 C to + 85 C |
| Series | SN74LVC138A |
| Technology | CMOS |
| Width | 3.91 mm |
| Brand | Texas Instruments |
| Logic Type | Decoders/Demultiplexers |
| Supply Current - Max | 0.01 mA |
| High Level Output Current | - 24 mA |
| Low Level Output Current | 24 mA |
| Maximum Clock Frequency | 100 MHz |
| Operating Supply Voltage | 1.65 V to 3.6 V |
| Product Type | Encoders, Decoders, Multiplexers & Demultiplexers |
| Factory Pack Quantity | 2500 |
| Subcategory | Logic ICs |
| Unit Weight | 0.004998 oz |
For more information, please refer to datasheet
Documents
| SN74LVC138ADR Datasheet |
More Information
The SN74LVC138A devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
