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Texas Instruments

TPA3244DDWR

TPA3244DDWR

Regular price $1.23 USD
Regular price Sale price $1.23 USD
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TPA3244DDWR Texas Instruments - Yeehing Electronics

60-W stereo, 120-W mono, 12- to 31.5-V supply, analog input Class-D audio amplifier, pad-down

Pricing (USD)

Quantity Unit Price
1 — 99 4.068
100 — 249 3.317
250 — 999 2.607
1,000 + 1.23

The above prices are for reference only.

Specifications

Manufacturer Texas Instruments
Product Category Audio Amplifiers
RoHS Y
Series TPA3244
Product Audio Amplifiers
Class Class-D
Output Power 110 W
Mounting Style SMD/SMT
Type Stereo
Package / Case HTSSOP-44
Audio - Load Impedance 4 Ohms
THD plus Noise 0.005 %
Supply Voltage - Max 30 V
Supply Voltage - Min 12 V
Minimum Operating Temperature 0 C
Maximum Operating Temperature + 70 C
Packaging Reel
Input Type Analog
Supply Type Single
Brand Texas Instruments
Number of Channels 4 Channel
Shutdown Shutdown
Moisture Sensitive Yes
Operating Supply Current 40 mA
Product Type Audio Amplifiers
PSRR - Power Supply Rejection Ratio 60 dB
Factory Pack Quantity 2000
Subcategory Audio ICs
Unit Weight 0.011912 oz

For more information, please refer to datasheet

Documents

TPA3244DDWR Datasheet

More Information

The TPA3244 device is a high performance Class-D power amplifier that enables true premium sound quality with Class-D efficiency. It features an advanced integrated feedback design and proprietary high-speed gate driver error correction (PurePath™ Ultra-HD). This technology allows ultra low distortion across the audio band and superior audio quality. With a 30-V power supply the device can drive up to 2 x 110 W peak into 4-Ω load and 2 x 60 W continuous into 8-Ω load and features a 2-VRMS analog input interface that works seamlessly with high performance DACs such as Burr-Brown PCM52xx DAC Family from TI (that is, PCM5242 / PCM5252). In addition to excellent audio performance, TPA3244 achieves both high power efficiency and very low power stage idle losses below 0.45 W. This is achieved through the use of 65 mΩ MOSFETs and an optimized gate driver scheme that achieves significantly lower idle losses than typical discrete implementations.

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