TPA3250D2DDWR


YeeHing #: Y002-TPA3250D2DDWR
Inventory: 5000

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Description

TPA3250D2DDWR Texas Instruments - Yeehing Electronics

70-W stereo, 140-W mono, 12- to 38-V supply, analog input Class-D audio amplifier, pad-down

Pricing (USD)

Quantity Unit Price
1 — 99 4.326
100 — 249 3.527
250 — 999 2.772
1,000 + 1.37

The above prices are for reference only.

Specifications

Manufacturer Texas Instruments
Product Category Audio Amplifiers
RoHS Y
Series TPA3250D2
Product Audio Amplifiers
Class Class-D
Output Power 70 W, 130 W
Mounting Style SMD/SMT
Type Audio Power Amplifier
Package / Case HTSSOP-44
THD plus Noise 0.005 %
Supply Voltage - Max 36 V
Supply Voltage - Min 12 V
Minimum Operating Temperature 0 C
Maximum Operating Temperature + 70 C
Packaging Reel
Input Type Analog
Brand Texas Instruments
Gain 20 dB
Number of Channels 2 Channel
Shutdown Shutdown
Moisture Sensitive Yes
Operating Supply Current 40 mA
Pd - Power Dissipation 600 mW
Product Type Audio Amplifiers
PSRR - Power Supply Rejection Ratio 60 dB
SNR - Signal to Noise Ratio 112 dB
Factory Pack Quantity 2000
Subcategory Audio ICs
Tradename PurePath
Unit Weight 0.011933 oz

For more information, please refer to datasheet

Documents

TPA3250D2DDWR Datasheet

More Information

The TPA3250 device is a high performance class-D power amplifier that enables true premium sound quality with class-D efficiency. It features an advanced integrated feedback design and proprietary high-speed gate driver error correction (PurePath™ Ultra-HD). This technology allows ultra low distortion across the audio band and superior audio quality. With a 32V power supply the device can drive up to 2 × 130 W peak into 4-Ω load and 2 × 70 W continuous into 8-Ω load and features a 2 VRMS analog input interface that works seamlessly with high performance DACs such as TI’s PCM5242. In addition to excellent audio performance, TPA3250 achieves both high power efficiency and very low power stage idle losses below 1 W. This is achieved through the use of 60 mΩ MOSFETs and an optimized gate driver scheme that achieves significantly lower idle losses than typical discrete implementations.

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